← Tanish Bengani
Interconnect

RTL NoC Node and Router

Interconnect · December 2025 · SystemVerilog

Fully synthesizable 6-node, 2-router network-on-chip.

  • Built a fully synthesizable 6-node, 2-router NoC with an inter-router pathway.
  • Handshake protocols and FSM locksteps for inter-thread communication.
  • Reusable fairness arbiter and FIFO submodules.