RTL RV32I CPU with Function-Level Macro-Op Fusion Accelerator
7-stage RISC-V pipeline with a custom accelerator for multiply emulation. 3rd for MIPS out of 35 teams.
- Ranked 3rd for MIPS and 5th for MIPS/Watt out of 35 teams with data-driven design. Achieved Pareto optimality.
- 7-stage pipeline with GSHARE branch prediction, I/D caches with I-side next-line prefetching, and decode forwarding.
- Accelerator dynamically detected the multiply emulation function and performed it in hardware instead while maintaining ISA compliance. Achieved up to 1.834x speedup on competition workloads.
- Implemented a randomized regression tester, which caught 2 bugs in the reference simulator.